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LTC4255 Quad Network Power Controller with I2C Compatible Interface
FEATURES
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DESCRIPTIO
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Controls Four Independent -48V Power Channels Each Channel has Separate Relay Drivers, ON/OFF Control, Short-Circuit Protection with Current Foldback, Open-Circuit Detection, and Power Good Indication Programmed via I2CTM Compatible Interface Five Bit Programmable Digital Address Allows Control of up to 32 LTC4255s (128 Channels) Interrupt on FAULT Output can be used to Eliminate Software Polling Programmable Current Limit and Open-Circuit Duration Periods Programmable Latchoff or Autoretry after ShortCircuit Faults Programmable Autoretry Duty Cycle
The LTC(R)4255 is a quad -48V network power controller with independent relay drivers and I2C compatible interface. Each channel can be turned on and off via software control, while providing short-circuit protection, opencircuit detection, and power good indication. The shortcircuit protection includes a current foldback feature to reduce power dissipation in the switch during shorts and start-up. The serial interface allows up to 128 channels to be controlled with only two digital lines. A FAULT output can be used as an interrupt line to eliminate fault detection by software polling. External switches and current sense resistors allow easy scaling of current and power dissipation levels and provide the maximum protection against voltage and current spikes. The LTC4255 is available in the 28-pin SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation. I2C is a trademark of Philips Electronics N.V.
APPLICATIO S
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IP Phone Systems DTE Power Distribution
TYPICAL APPLICATIO
12V
0.1F
VCC SCL SDA FAULT AD0 AD1 AD2 AD3 AD4 DGND AGND VEE SENSE1 GATE1 RELAY3 RELAY4 OUT1 SENSE2 GATE2 OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4 100k Q1 RS2 0.33 Q2 RS3 0.33 Q3 Q1, Q2, Q3, Q4: FDC3612 RELAYS: V23079 SERIES RS4 0.33
4255 TA01
LTC4255
-48V
RS1 0.1F 0.33
100k
100k
Q4
4255f
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RELAY1 RELAY2 100k
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1
LTC4255
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW FAULT SCL SDA AD4 AD3 AD2 AD1 AD0 RELAY1 1 2 3 4 5 6 7 8 9 28 OUT1 27 GATE1 26 SENSE1 25 OUT2 24 GATE2 23 SENSE2 22 VEE 21 OUT3 20 GATE3 19 SENSE3 18 OUT4 17 GATE4 16 SENSE4 15 AGND
Supply Voltages VCC to DGND ....................................................... 18V VEE to AGND ...................................................... -80V DGND to AGND ................................................... 5V Digital Pin Voltages SCL, SDA, FAULT ........................ DGND - 0.3V to 6V AD0-4 ....................................... DGND - 0.3V to 5.5V Relay Driver Output Voltage RELAY1-4 (Note 5) ...... DGND -0.3V to DGND + 15V Analog Voltages SENSE1-4 ............................... VEE - 0.3V to VEE + 1V OUT1-4 .................................. VEE - 80V to VEE + 80V Operating Temperature Range LTC4255C ............................................... 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC4255CG
RELAY2 10 RELAY3 11 RELAY4 12 DGND 13 VCC 14
G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125C, JA = 90C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 12V, VEE = -48V, AGND = DGND = 0V (Note 2)
SYMBOL VCC ICC VEE IEE VGND VLKO VGATE IGATE VSC VOC VPG IOUT VOLR VCLAMPR VOLD PARAMETER Positive Supply Voltage Positive Supply Current Negative Supply Voltage Negative Supply Current DC Ground Difference VEE Undervoltage Lockout External Gate Voltage (VGATE - VEE) GATE Pin Output Current Short-Circuit Sense Voltage Open-Circuit Sense Voltage Power_OK Threshold Voltage OUT Pin Current Relay Driver Output Low Voltage Relay Driver Clamp Voltage Digital Output Low Voltage IGATE = -1A GATE On, VGATE = VEE GATE Off, VGATE = VEE + 5V (VSENSE - VEE), VOUT - VEE = 0V (VSENSE - VEE) (VOUT - VEE) VOUT = VEE (VRELAY - DGND), IRELAY = 50mA, RELAY On (VRELAY - DGND), IRELAY = 50mA, RELAY Off (Note 5) SDA, FAULT, I = 3mA
q q q q
ELECTRICAL CHARACTERISTICS
DC Characteristics
CONDITIONS VCC Referenced to DGND Relays Off All Relays On VEE Referenced to AGND AGND - DGND (Note 3)
MIN 10.8
TYP 12 2.1 10 -48 -1.9
MAX 13.2 3 15 -72 -3 5
UNITS V mA mA V mA V V V A A mV mV V A V V V
-5 -27 10 -30 30 125 1 1 13 -50 50 150 3 2 -1.4
15 -70 80 170 4.5 3 0.3
18
24 0.4
2
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LTC4255
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 12V, VEE = -48V, AGND = DGND = 0V
SYMBOL VILD VIHD RPU tCL PARAMETER Digital Input Low Voltage Digital Input High Voltage AD0 to AD4 Pullup Resistors to 5V Current Limit Filter Time B5 = 0, B4 = 0, Figure 2 B5 = 0, B4 = 1 B5 = 1, B4 = 0 B5 = 1, B4 = 1 B7 = 0, B6 = 0 B7 = 0, B6 = 1 B7 = 1, B6 = 0 B7 = 1, B6 = 1 Figure 3 Figure 4 B3 = 0 B3 = 1 (Note 3) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4)
q q q q q q q q q q q q q q q q q q q q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS SCL, SDA SCL, SDA
q q
MIN 2.4 30 4.8 9.6 19.2 76.8 50 104 213 433 9.6 9.6 0.78 5.5 1.3 600 1.3 600 150 200 600 600
TYP
MAX 0.8
UNITS V V k ms ms ms ms ms ms ms ms ms ms % % kHz s ns s ns ns ns ns ns
50 6 12 24 96 62 130 267 541 18 18 0.83 6
90 7.2 14.4 28.8 115.2 74 156 320 649 28.8 28.8 0.89 6.7 400
AC Characteristics
tOCD
Open-Circuit Enable Delay After Power_OK
tOCF tOD DCR tSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 tr tf
Open-Circuit Filter Time Turn-On Delay Time Retry Duty Cycle Clock Frequency Bus Free Time Start Hold Time SCL Low Time SCL High Time Data Hold Time Data Setup Time Start Setup Time Stop Setup Time Stop to Fault Clear SCL, SDA Rise Time SCL, SDA Fall Time
300 20 20 300 150
ns ns ns
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Note 3: Guaranteed by design, not subject to test. Note 4: Values referred to VILD and VIHD. Note 5: A Zener diode clamps the relay drivers at 18V (RELAY 1-4).
4255f
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LTC4255 TYPICAL PERFOR A CE CHARACTERISTICS
ICC vs VCC (Relays Off)
1.290 TA = 25C
9.8 9.6 9.4 ICC (mA)
1.280
ICC (mA)
ICC (mA)
1.270
1.260
1.250
1.240 10.8
11.3
12.3 11.8 VCC (V)
ICC vs Temperature (Relays On)
9.6 9.5 9.4 9.3
ICC (mA)
VCC = 12V
9.2 9.1 9.0
IEE (mA)
-1.2
-1.6
8.9 8.8 -50 -25 50 TEMPERATURE (C) 0 25 75 100
4255 G04
-2.0 -80
IEE (mA)
VSC vs VOUT
160 140 120
VSC (mV)
VOC (mV)
VSC (mV)
100 80 60 40 20 0 -50 -40 -20 -30 VOUT (V) -10 0
4255 G07
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UW
12.8 TA = 25C
ICC vs VCC (Relays On)
TA = 25C
1.34 1.32 1.30 1.28 1.26 1.24
ICC vs Temperature (Relays Off)
VCC = 12V
9.2 9.0 8.8 8.6 10.8
1.22 1.20 -50
13.3
4255 G01
11.3
11.8 12.3 VCC (V)
12.8
13.3
4255 G02
-25
0 25 50 TEMPERATURE (C)
75
100
4255 G03
IEE vs VEE
0
-1.88
IEE vs Temperature
VEE = -48V
TA = 25C
-1.90
-0.4
-0.8
-1.92
-1.94
-1.96
-60
-40 VEE (V)
-20
0
4255 G05
-1.98 -50
-25
0 25 50 TEMPERATURE (C)
75
100
4255 G06
VSC vs Temperature
165 160 155 150 145 140 135 -50 VOUT = VEE 3.20 3.15 3.10 3.05 3.00 2.95
VOC vs Temperature
-25
0 25 50 TEMPERATURE (C)
75
100
4255 G08
2.90 -50
-25
25 50 0 TEMPERATURE (C)
75
100
4255 G09
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LTC4255 TYPICAL PERFOR A CE CHARACTERISTICS
IOUT vs VOUT
0 -0.2 -0.4
IGATE (A)
IOUT (A)
IOUT (A)
-0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -50 -40 -20 -30 VOUT (V)
IGATE vs Temperature
65 60 55 IGATE (A)
VGATE (V)
GATE OFF VGATE = VEE + 5V
13.0 12.8 12.6 12.4 12.2 -50
ISENSE (A)
50 45 40 35 -50
-25
0 25 50 TEMPERATURE (C)
VEE Undervoltage Lockout vs Temperature
-26 VEE UNDERVOLTAGE LOCKOUT (V) -27 -28
VOL (V)
RPU (k)
-29 -30 -31 -32 -50
-25
0 25 50 TEMPERATURE (C)
UW
TA = 25C VEE = -48V -10
IOUT vs Temperature
2.0 1.8 1.6 1.4 1.2 1.0 0.8 -50 VOUT = VEE
-44 -46 -48 -50 -52 -54 -56
IGATE vs Temperature
GATE ON VGATE = VEE
0
4255 G10
-25
0 25 50 TEMPERATURE (C)
75
100
4255 G11
-58 -50
-25
50 25 0 TEMPERATURE (C)
75
100
4255 G12
VGATE vs Temperature
13.6 13.4 13.2
-42 -43 -44 -45 -46 -47
ISENSE vs Temperature
VSENSE = VEE
75
100
4255 G13
-25
50 25 0 TEMPERATURE (C)
75
100
4255 G14
-48 -50
-25
0 25 50 TEMPERATURE (C)
75
100
4255 G15
Relay Driver Output Low Voltage (VOLR) vs Temperature
0.170 0.165 0.160 0.155 0.150 0.145 0.140 0.135 IRELAY = 50mA 60 59 58 57 56 55 54 53 52 -25 25 50 0 TEMPERATURE (C) 75 100
4255 G17
AD0-4 Pullup Resistors to 5V (RPU) vs Temperature
75
100
4255 G16
0.130 -50
51 -50
50 0 TEMPERATURE (C)
100
4255 G18
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LTC4255
PI FU CTIO S
FAULT (Pin 1): Open-Drain FAULT Output. Pulls low when a short-circuit or open circuit fault occurs. The signal can be used to generate a fault condition interrupt to the host controller eliminating the need for continuous software polling. SCL (Pin 2): Serial Interface Clock Input. It requires a resistor or current source that pulls up to a supply that is less than 6V. SDA (Pin 3): Serial Interface Data Input and Output. It requires a resistor or current source that pulls up to a supply that is less than 6V. AD0-4 (Pins 4,5,6,7,8): Serial Interface Address Inputs. Connect to DGND for a low, float or connect to 3.3V or 5V supply for a high. RELAY1-4 (Pins 9,10,11,12): Relay Driver Outputs. Open collector capable of sinking 50mA to within 0.3V of DGND. An internal 18V clamp to DGND will protect the part when the relay is turned off. DGND (Pin 13): Digital Ground. Return for digital logic and relay drivers. Must be within 5V of AGND. VCC (Pin 14): 12V Supply Input. Powers the digital section and relay drivers. Bypass with a 0.1F capacitor to DGND. AGND (Pin 15): Analog Ground. SENSE1-4 (Pins 16,19,23,26): Current Sense Inputs. Monitors the FET current with a sense resistor placed between SENSE and VEE. When the voltage across the sense resistor reaches the short-circuit sense voltage, the GATE pin voltage will be lowered to maintain a constant current in the FET. At the same time, the current limit timer will be started. If the short-circuit condition persists for the duration of the current limit timer period, the FET will be turned off. The short-circuit sense voltage is lowered to reduce the FET power dissipation when the voltage at the associated OUT pin is within 18V of AGND. If the open-circuit enable bit is set and the voltage across the sense resister remains below the open-circuit sense voltage for longer than tOCF, the open-circuit filter time, then the FET will be turned off. GATE1-4 (Pins 17,20,24,27): Gate Drive Outputs. When the FET is turned on, a 50A pull-up current source is connected to the pin. The gate voltage is clamped to 13V(typ) above VEE. During a short-circuit condition, the GATE pin voltage will be driven to a lower voltage to maintain a constant current in the FET. OUT1-4 (Pins 18,21,25,28): Output Voltage Monitor Inputs. A current limit foldback feature limits the power dissipation in the FET by reducing the short-circuit current when the voltage at the OUT pin is between AGND and AGND - 18V. The Power_OK bit is set when the voltage from OUT to VEE is less than about 2V. VEE (Pin 22): -48V Supply Input.
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LTC4255
REGISTER DEFI ITIO S
Register 1: Control Register ( Write Only) A0: Switch 1 Enable. Logic high turns on Port 1 switch, logic low turns off the Port 1 switch. A1: Switch 2 Enable. Logic high turns on Port 2 switch, logic low turns off Port 2 switch. A2: Switch 3 Enable. Logic high turns on Port 3 switch, logic low turns off Port 3 switch. A3: Switch 4 Enable. Logic high turns on Port 4 switch, logic low turns off Port 4 switch. A4: Relay 1 Enable. Logic high turns on Port 1 relay, logic low turns off Port 1 relay. A5: Relay 2 Enable. Logic high turns on Port 2 relay, logic low turns off Port 2 relay. A6: Relay 3 Enable. Logic high turns on Port 3 relay, logic low turns off Port 3 relay. A7: Relay 4 Enable. Logic high turns on Port 4 relay, logic low turns off Port 4 relay. The default setting is all bits set low. Register 2: Setup Register (Write Only) B0: Fault Clear Bit. Logic high clears any fault bits that are set. B1: Autoretry Enable Bit. Logic high enables autoretry following short-circuit faults. Logic low disables autoretry. B2: Open-Circuit Detect Enable Bit. Logic high enables and logic low disables open-circuit fault detection. B3: Retry Duty Cycle Select Bit. Logic high sets the autoretry duty cycle to 6%. Logic low sets the autoretry duty cycle to 0.83%. When autoretry is not enabled (B1 = low), the switch turn-on after A0 to A3 are set to high will be delayed to enforce the selected retry duty cycle. B4: Current Limit Timer Select Bit 0. The current limit timer select bits configure tCL, the time a current limit must be sustained before a short-circuit fault occurs. (See tCL in AC Characteristics.) B5: Current Limit Timer Select Bit 1. The current limit timer select bits configure tCL, the time a current limit must be sustained before a short-circuit fault occurs. (See tCL in AC Characteristics.) B6: Open-Circuit Enable Delay Timer Select Bit 0. The open-circuit enable delay timer select bits configure tOCD, the time following a Power_OK condition when no opencircuit faults will be generated. ( See tOCD, in AC Characteristics.) B7: Open-Circuit Enable Delay Timer Select Bit 1. The open-circuit enable delay timer select bits configure tOCD, the time following a Power_OK condition when no opencircuit faults will be generated. ( See tOCD, in AC Characteristics.) The default setting is all bits set low. Register 3: Status Register 1 (Read Only) C0: Power_OK for Port 1. Logic high indicates switch 1 is on. C1: Power_OK for Port 2. Logic high indicates switch 2 is on. C2: Power_OK for Port 3. Logic high indicates switch 3 is on. C3: Power_OK for Port 4. Logic high indicates switch 4 is on. C4: Reserved. Logic high. C5: Reserved. Logic low. C6: Reserved. Logic low. C7: Reserved. Logic low.
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LTC4255
REGISTER DEFI ITIO S
Register 4: Status Register 2 (Read Only) D0: Current Limit Fault Status for Port 1. Logic high indicates a short-circuit has been detected on Port 1. D1: Current Limit Fault Status for Port 2. Logic high indicates a short-circuit has been detected on Port 2. D2: Current Limit Fault Status for Port 3. Logic high indicates a short-circuit has been detected on Port 3. D3: Current Limit Fault Status for Port 4. Logic high indicates a short-circuit has been detected on Port 4. D4: Open-Circuit Fault Status for Port 1. Logic high indicates an open-circuit has been detected on Port 1. D5: Open-Circuit Fault Status for Port 2. Logic high indicates an open-circuit has been detected on Port 2. D6: Open-Circuit Fault Status for Port 3. Logic high indicates an open-circuit has been detected on Port 3. D7: Open-Circuit Fault Status for Port 4. Logic high indicates an open-circuit has been detected on Port 4.
TEST TI I G
t3 t4 SCL t2 SDA t1 FAULT
4255 F01
VSC VSENSE TO VEE 0V tCL
FAULT
4255 F02
Figure 2. Current Limit Timing
SCL
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tr tf t5 t6 t7 t8 t9
Figure 1. 2-Wire Interface Timing
VSENSE TO VEE 0V
VOC
FAULT tOCF
4255 F03
Figure 3. Open-Circuit Filter Timing
SDA GATE
AO
ACK STOP BIT tOD
4255 F04
Figure 4. Turn-On Delay
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LTC4255
TI I G DIAGRA S
SCL
SDA
0
1
AD4 AD3 AD2 AD1 AD0 R/W ACK A7
START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE
SCL
SDA
0
1
START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE
SCL
SDA
0
1
AD4 AD3 AD2 AD1 AD0 R/W ACK A7
START BY MASTER FAULT
FRAME 1 SERIAL BUS ADDRESS BYTE
W
UW
A6
A5
A4
A3
A2
A1
A0 ACK B7
B6
B5
B4
B3
B2
B1
B0
ACK
ACK BY SLAVE FRAME 2 CONTROL BYTE
ACK BY SLAVE
STOP BY MASTER. INTERNAL DATA LATCHES UPDATED FRAME 3 SETUP BYTE
4255 F05
Figure 5. Writing to the Control and Setup Registers
AD4 AD3 AD2 AD1 AD0 R/W ACK A7
A6
A5
A4
A3
A2
A1
A0
ACK
ACK BY SLAVE FRAME 2 CONTROL BYTE
ACK BY SLAVE
STOP BY MASTER. INTERNAL DATA LATCHES UPDATED
4255 F06
Figure 6. Writing to the Control Register Only
A6
A5
A4
A3
A2
A1
A0 ACK B7
B6
B5
B4
B3
B2
B1
B0
ACK
ACK BY SLAVE
ACK BY SLAVE
STOP BY MASTER. INTERNAL DATA LATCHES UPDATED
FRAME 2 CONTROL BYTE
FRAME 3 SETUP BYTE
4255 F07
Figure 7. Clearing the FAULT Signal
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LTC4255
TI I G DIAGRA S
SCL
SDA
0
1
AD4 AD3 AD2 AD1 AD0 R/W ACK C7
START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE
SCL
SDA
0
10
W
UW
C6
C5
C4
C3
C2
C1
C0 ACK D7
D6
D5
D4
D3
D2
D1
D0 ACK
ACK BY SLAVE FRAME 2 STATUS BYTE #1
ACK BY MASTER FRAME 3 STATUS BYTE #2
NO ACK BY MASTER
STOP BY MASTER
4255 F08a
Figure 8a. Reading Both Status Registers
1
AD4 AD3 AD2 AD1 AD0 R/W ACK C7
C6
C5
C4
C3
C2
C1
C0 ACK
START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE
ACK BY SLAVE FRAME 2 STATUS BYTE#1
ACK BY MASTER
STOP BY MASTER
4255 F08b
Figure 8b. Reading Status Register #1 Only
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LTC4255
APPLICATIO S I FOR ATIO
Normal Power-Up Using channel 1 as an example, a normal power-up cycle begins when the switch 1 enable bit (A0) and relay 1 enable bit (A4) are set high and then latched into the chip by a STOP bit on the serial interface (point A, Figure 9). The RELAY1 output turns on immediately and energizes an optional relay connecting the AGND and OUT1 pins to the cable. After a fixed delay of approximately 18ms (tOD), the GATE1 pin will start to pull high (point B). When the threshold voltage of the FET is reached, current will begin flowing in the external FET (point C). The voltage at the OUT1 pin will then fall at a rate determined by the current limit and the output load capacitance. Because the current limit is lower when the OUT1 pin is near AGND due to the foldback circuit, the voltage will fall slowly at first, then get faster. At the same time, the current limit timer will start. The OUT1 voltage must reach its final value and the analog current limit circuit must turn off before the current limit timer expires, or a current limit fault will be detected and the FAULT pin will be pulled low.
SCL
SDA SHORT-CIRCUIT STATUS (D0) OPEN-CIRCUIT STATUS (D4) POWER_OK (C0) FAULT
AO
ACK STOP BIT
RELAY1 FET TURNS ON GATE1
OUT1
Figure 9. Normal Power-Up and Power-Down Sequence on Channel 1
4255f
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When the voltage at OUT1 is within 2V of VEE, the Power_OK (C0) bit will be set (point D) and the open-circuit enable delay timer started. As long as the load current turns on before the open-circuit enable delay timer expires, the FAULT pin will remain in a high impedance state and the current limit fault status bit (D0) and open-circuit fault status bit (D4) bits will remain low, thus completing a normal power-up sequence. The Power_OK bit will remain high until the switch is turned off by setting the switch enable bit (AO) low or a short-circuit or opencircuit condition turns off the switch. A normal power-down sequence begins when the switch enable bit (A0) and relay enable bit (A4) are cleared and then latched into the chip by a STOP bit on the serial interface (point E). The RELAY1 pin will go into a high impedance state and the inductive voltage spike from the primary coil will be clamped at about 18V. The relay will typically disengage several milliseconds later. At the same time, the GATE1 pin will be pulled low by a 50A current source, the FET will turn off, and the Power_OK bit will be cleared.
AO ACK POWER OK A tOD B C D E
4255 F09
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LTC4255
APPLICATIO S I FOR ATIO
Power-Up with No Load When a channel powers-up with no load, the initial sequence is the same as the normal case. When the VOUT1 voltage is within the power good threshold, the Power_OK bit is set (point D, Figure 10) and the open-circuit enable delay timer started. The duration of the timer can be programmed via bits B6-B7. When the open-circuit enable timer expires (tOCD, point E), the open-circuit detector is enabled if the global opencircuit detect enable bit (B2) has been set. When the voltage across the sense resistor is less than 3mV(typ) for at least 18ms (tOCF), the FET will be turned off, and the
SCL
SDA SHORT-CIRCUIT STATUS (D0) OPEN-CIRCUIT STATUS (D4) POWER_OK (C0) FAULT
AO
ACK STOP BIT
RELAY1 FET TURNS ON GATE1 OPEN CIRCUIT TIMER EXPIRES OUT1 POWER OK POWER OK
A tOD
B
Figure 10. Power-Up Sequence with No Load on Channel 1
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open-circuit fault status bit (D4) will be set (point E). The FAULT pin will pull low to generate an interrupt to the processor which can then read the status register to determine which channel faulted. When the fault clear bit (B0) is set during a write cycle via the 2-wire interface (point F), the FAULT pin goes into a high impendance state, the open-circuit fault status bit (D4) is cleared, and the channel is allowed to turn back on if the relay 1 enable (A4) and switch 1 (AO) enable bits are set (point G.) The channel is always turned off after an open-circuit fault detection and not allowed to automatically restart.
BO ACK FAULT CLEARED OPEN CIRCUIT DETECTED C D tOCD E F G H
4255 F10
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LTC4255
APPLICATIO S I FOR ATIO
Power-Up into a Short-Circuit When a channel powers-up with a shorted load, the RELAY1 pin will pull low immediately and the GATE1 pin will start to pull high (point B Figure 11) after a turn-on delay (tOD). When the FET turns on at point C, the current will reach a constant value and the programmable current limit timer (tCL) will start. The current limit timer is programmed via bits B4 to B5. When the current limit timer expires, the GATE1 and FAULT pins will pull low, the current limit fault status bit (D0) will be set, and the retry timer (tR) started (point D).
SCL
SDA SHORT-CIRCUIT STATUS (D0) OPEN-CIRCUIT STATUS (D4) POWER_OK (C0) FAULT
AO
ACK STOP BIT
RELAY1 FET TURNS ON GATE1 CL TIMER EXPIRES CHANNEL LATCHES OFF
OUT1 FET CURRENT A tOD B C tCL D tR E F G H I
4255 F11
Figure 11. Power-Up Sequence with Shorted Load on Channel 1 with Autoretry Disabled
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If the autoretry enable bit (B1) is not set, the channel will remain off until the fault is cleared by setting the fault clear bit (B0) and the channel is turned back on by setting the switch enable bit (A0) and the relay enable bit (A4) (point F). If the fault clear bit (B0) is set before the retry timer expires (point E) the channel turn-on will be delayed until the timer expires to enforce the maximum retry duty cycle (DCR). This duty cycle is programmable via bit B3 and sets the maximum ratio of the FET on-time to off-time under a short-circuit condition.
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DC R =
tCL tCL + tR
BO
ACK STOP BIT
FAULT CLEARED
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LTC4255
APPLICATIO S I FOR ATIO
If the autoretry enable bit (B1) is set, then the channel will automatically restart after the retry delay timer expires (Figure 12, point E). If the channel successfully powers up after an autoretry, the Power_OK bit (CO) will be set. However, FAULT will continue to pull down and the shortcircuit bit (DO) will remain high until the fault is cleared by setting the FAULT clear bit (BO). In the case of a short-circuit occuring after a normal power-up, high rates of change of current (high di/dt) through the inductance of the cable or even the traces on the PCB can cause the voltages at OUT1-4 to overshoot. A 100k resistor should be placed between the drains of the FETs and the OUT1-4 pins to limit the energy absorbed by the LTC4255 if the drains of the FETs exceed OUT1-4's absolute maximum voltage rating. Also, if the FETs are not capable of safely absorbing this energy, high-speed
SCL
SDA SHORT-CIRCUIT STATUS (D0) OPEN-CIRCUIT STATUS (D4) POWER_OK (C0) FAULT
AO
ACK STOP BIT
RELAY1
GATE1
FET TURNS ON
OUT1 FET CURRENT A tOD B C tCL D tR E F G H
4255 F12
Figure 12. Power-Up Sequence with Shorted Load on Channel 1 with Autoretry Enabled
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Schottky diodes should be added between the drains of the FETs and AGND using a layout that minimizes the trace lengths between the parts. Address Selection The lower 5 bits of the serial interface address can be set by the address selection pins AD0 to AD4 with AD0 being the least significant bit. The upper two bits are preset to AD5 = high and AD6 = low. To force an address bit to low, the address selection pin should be connected to DGND. To force an address bit to high, the address selection pin can be left floating and an internal pull-up resistor will pull the pin up to the internal digital supply voltage (typically 5V). If more noise immunity is needed, the pin can be connected directly to a 5V or 3.3V external supply.
BO ACK STOP BIT FAULT CLEARED CL TIMER EXPIRES AUTO-RESTART INITIATED CL TIMER EXPIRES
4255f
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LTC4255
APPLICATIO S I FOR ATIO
Relay Drivers The four relay drivers have an open collector NPN transistor with the ability to sink 50mA to within 0.3V of DGND (Figure 13).
DRIVE CIRCUITRY
Figure 13. Relay Driver Output
PACKAGE DESCRIPTIO
G Package 28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
9.90 - 10.50* (.390 - .413) 1.25 0.12 28 27 26 25 24 23 22 21 20 19 18 17 16 15
7.8 - 8.2
0.42 0.03 RECOMMENDED SOLDER PAD LAYOUT 5.00 - 5.60** (.197 - .221)
0.09 - 0.25 (.0035 - .010)
0.55 - 0.95 (.022 - .037)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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An 18V Zener diode connected to DGND is provided to protect against the inductive kickback of the coil when the NPN transistor is turned off.
3V TO 12V RELAY 18V DGND
4255 F13
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5.3 - 5.7
7.40 - 8.20 (.291 - .323)
0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2.0 (.079)
0 - 8
0.65 (.0256) BSC
0.22 - 0.38 (.009 - .015)
0.05 (.002)
G28 SSOP 0802
4255f
15
LTC4255
TYPICAL APPLICATIO
Typical Application Using Schottky Diodes to Protect FETs
SCL SDA FAULT AD0 AD1 AD2 AD3 AD4 DGND AGND VEE SENSE1 GATE1 RELAY3 RELAY4 OUT1 SENSE2 GATE2 OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4 100k Q1 100k 100k 100k LTC4255 RELAY1 RELAY2
-48V
RS1 0.1F 0.33
Q1, Q2, Q3, Q4: FDC3612 (FAIRCHILD) SCHOTTKY DIODES: MBRS1100T3 (ON SEMI) RELAYS: V23079 SERIES (TYCO/POTTER AND BRUMFIELD)
RELATED PARTS
PART NUMBER LTC1694 LT4250 LTC4251 DESCRIPTION I2C/SMBus Accelerator Negative Voltage Hot Swap Controller in SO-8 Negative Voltage Hot Swap Controller in SOT-23 COMMENTS Active Pull-Up Improves Rise Time, Ensures Data Integrity Active Current Limiting, Supplies from -20V to -80V Active Current Limiting, Floating Supplies from -15V Isolates SDA, SCL Lines from Output/Allows 3.3V to 5V Level Translation
LTC4300-1/LTC4300-2 Hot Swappable 2-Wire Bus Buffer
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507 q www.linear.com
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12V 0.1F VCC RS2 0.33 Q2 RS3 0.33 Q3
4255 TA01
RS4 0.33
Q4
4255f LT/TP 0203 2K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2002

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